.include "basicloader.asm"
	.include "chameleon_test_chars.asm"
	.code
	jmp main

COREID      = $04
ORGCFGENA   = $10     ; Startup value of CFGENA
ORGCFGTUR   = $11     ; Startup value of CFGTUR
ORGCFGREG   = $12     ; Startup value of CFGREG
REPEATCNT   = $20     ; Repeat a test
CMP_TEMP    = $21     ; Temp storage to compare two values
STRINGL     = $f9
STRINGH     = $fa
COLOR       = $fb
COLORL      = $fc
COLORH      = $fd
CURSORL     = $fe
CURSORH     = $ff	
REGENPOS    = $0400
CHARPOS     = $3800
RASTER      = $D012
VIC_VMCB    = $D018
VERIDX      = $D0A8
VERDAT      = $D0A9
CFGTUR      = $D0F3
CFGREG      = $D0FA
CFGDIS      = $D0FD
CFGENA      = $D0FE
CFGRTI      = $D0FF
CIA1_TALO   = $DC04
CIA1_TAHI   = $DC05
CIA1_TBLO   = $DC06
CIA1_TBHI   = $DC07
CIA1_TODTEN = $DC08
CIA1_TODSEC = $DC09
CIA1_TODMIN = $DC0A
CIA1_TODHR  = $DC0B
CIA1_CRA    = $DC0E
CIA1_CRB    = $DC0F
COLORRAM    = $D800

BANK_RAM = 0
BANK_VIC = 1
BANK_SID = 2
BANK_CFG = 3
BANK_MMU = 4
BANK_UNK = 5

DEF_COLOR = 14
GRN_COLOR = 5
RED_COLOR = 2

	.macro SPACES nr
	ldx	#nr
	jsr	print_spaces
	.endmacro
	
	.macro STRING addr
		ldx	#<addr
		ldy #>addr
		jsr	printstr
	.endmacro

	.macro	BANK_RESULT bank_a, print_a
	ldx	#<bank_a
	ldy	#>bank_a
	lda	#>print_a
	jsr	printhex
	lda	#<print_a
	jsr	printhex
	jsr	bank_result_line
	.endmacro

main:
	; Don't want interrupts when banking etc.
	sei
	
	lda	CFGENA
	sta	ORGCFGENA

	; Set position of regen-buffer and character definitions
	lda	#(REGENPOS/1024)*16 + (CHARPOS/1024)
	sta	VIC_VMCB
	
	lda	#DEF_COLOR
	sta	COLOR
	
	jsr	clear_screen

	lda	#42
	sta	CFGENA
	lda	CFGTUR
	sta ORGCFGTUR
	lda	CFGREG
	sta ORGCFGREG
	
	; Enable all Chameleon registers
	lda	#$ff
	sta	CFGREG
	
	jsr	show_coreid
	jsr	show_version
	jsr	show_startup_values
	jsr	test_cfgena
	
	SPACES 40
	jsr backup_d700
	jsr	test_cfgreg
	jsr restore_d700
;	SPACES 40
	jsr	test_turbo
	jsr	test_clkspeed
	STRING done_str
	
wait_key:
	lda $dc01
	cmp #$ef
	bne wait_key
	jmp main

	;
	; Show coreID number
show_coreid:
	STRING coreid_str
	lda	CFGENA
	sta	COREID
	jmp	printhex

	;
	; Show core version number
show_version:
	STRING version_str
	ldx	#0
corever1:
	stx	VERIDX
	lda	VERDAT
	jsr	print_char
	inx
	cpx	#16
	bne	corever1
	lda	#39
	jsr	print_char
	jmp space

	;
	; Test the CFGENA register and the two disable registers around it.
test_cfgena:
	STRING test_cfgena_str

	; Disable configuration registers by writing to CFGENA
	lda	#$ff
	sta	CFGENA
	lda	CFGENA
	cmp	#$ff
	jsr	redgreen_hex
	jsr	space

	; Check influence read/write of CFGRTI on configuration mode
	lda	#42
	sta	CFGENA
	lda	CFGRTI			; load should not disable config mode
	cmp	#$40
	jsr	redgreen_hex
	lda	CFGENA
	cmp	COREID
	jsr	redgreen_hex
	sta	CFGRTI			; store should disable config mode
	lda	CFGENA
	cmp	#$FF
	jsr	redgreen_hex
	lda	CFGDIS
	cmp	#$FF
	jsr	redgreen_hex
	lda	CFGRTI
	cmp	#$FF
	jsr	redgreen_hex
	jsr	space

	; Check influence read/write of CFGDIS on configuration mode
	lda	#42
	sta	CFGENA
	lda	CFGDIS			; load should not disable config mode
	jsr	printhex
	lda	CFGENA
	cmp	COREID
	jsr	redgreen_hex
	sta	CFGDIS			; store should disable config mode
	lda	CFGENA
	cmp	#$FF
	jsr	redgreen_hex
	lda	CFGDIS
	cmp	#$FF
	jsr	redgreen_hex
	lda	CFGRTI
	cmp	#$FF
	jsr	redgreen_hex
	SPACES 3
	rts

show_startup_values:
	STRING startup_str
	lda	ORGCFGENA
	jsr	printhex
	STRING startup_cfgtur_str
	lda	ORGCFGTUR
	jsr	printhex
	STRING startup_cfgreg_str
	lda	ORGCFGREG
	jsr	printhex
	SPACES 3
	rts

test_cfgreg:
	STRING test_cfgreg_str
	SPACES 27

	; Enter configuration mode for this test
	lda	#42
	sta	CFGENA
	SPACES 4
	
	lda	#$80
	ldx	#$09
test_cfgreg1:
	dex
	pha
	pha
	pha
	sta	CFGREG
	jsr space
	jsr space
	pla
	jsr	printhex
	pla
	jsr	bank_test
	pla
	lsr
	cpx	#$00
	bne	test_cfgreg1
;	jsr	space

	BANK_RESULT bank_d000, $d000
	BANK_RESULT bank_d040, $d040
	BANK_RESULT bank_d080, $d080
	BANK_RESULT bank_d0c0, $d0c0
	BANK_RESULT bank_d100, $d100
	BANK_RESULT bank_d200, $d200
	BANK_RESULT bank_d300, $d300
	BANK_RESULT bank_d400, $d400
	BANK_RESULT bank_d500, $d500
	BANK_RESULT bank_d600, $d600
	BANK_RESULT bank_d700, $d700
	rts
	
bank_result_line:
	stx	bank_result_lda+1
	sty	bank_result_lda+2
	lda	bank_result_lda+1
	clc
	adc	#$09
	sta	bank_result_cmp+1
	lda	bank_result_lda+2
	adc	#$00
	sta	bank_result_cmp+2

	ldy	#$09
bank_result_line1:
	dey
	ldx	#GRN_COLOR
	stx	COLOR
bank_result_lda:
	lda	bank_d000,y
bank_result_cmp:
	cmp	bank_d000,y
	beq	bank_result_ok
	ldx	#RED_COLOR
	stx	COLOR
bank_result_ok:
	clc
	rol
	rol
	tax
	.repeat 4
	lda	bank_type,x
	jsr	print_char
	inx
	.endrep
	ldx	#DEF_COLOR
	stx	COLOR
	cpy	#$00
	bne	bank_result_line1
	rts

bank_test:
	lda	#$00
	sta	STRINGL
	lda	#$D0
	sta	STRINGH
	jsr	bank_run_test
	sta	bank_d000,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d100,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d200,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d300,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d400,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d500,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d600,x
	inc	STRINGH
	jsr	bank_run_test
	sta	bank_d700,x

	; For these addresses only run checks as writing will possibly currupt config registers.
	lda	#$40
	sta	STRINGL
	lda	#$D0
	sta	STRINGH
	jsr	bank_test_check
	sta	bank_d040,x
	lda	#$80
	sta	STRINGL
	jsr	bank_test_check
	sta	bank_d080,x
	lda	#$C0
	sta	STRINGL
	jsr	bank_test_check
	sta	bank_d0c0,x
	rts

bank_run_test:
	jsr	bank_test_pattern
	jmp	bank_test_check

bank_test_pattern:
	ldy	#$00
	lda	#$11
	sta	(STRINGL),y
	iny
	lda	#$22
	sta	(STRINGL),y
	iny
	lda	#$33
	sta	(STRINGL),y
	iny
	lda	#$44
	sta	(STRINGL),y
	; Write non-ascii code at offet 29. This is VERDAT register in D080-D0BF area
	; Can detect VIC vs RAM vs MMU. Should read back as F9 in VIC (color register), 29 when RAM and anything else when VERDAT.
	ldy	#$29
	lda	#$29
	sta	(STRINGL),y
	ldy	#$3E
	lda	#$1F
	sta	(STRINGL),y
	iny
	sta	(STRINGL),y
	rts

bank_test_check:
	ldy	#$00
	lda	(STRINGL),y
	cmp	#$1F			; Check for last written value in SID
	beq	bank_check_sid
	iny
	lda	(STRINGL),y
	cmp	#$22
	bne	bank_is_unknown
	ldy	#$29
	lda	(STRINGL),y
	cmp	#$29
	beq	bank_is_ram
	cmp	#$F9
	bne	bank_is_mmu
	ldy	#$3F
	lda	(STRINGL),y
	cmp	#$FF
	beq	bank_is_vic
	cmp	#$40			; Check for RTI on D0FF
	beq	bank_is_cfg
	bne	bank_is_unknown

bank_check_sid:
	iny
	lda	(STRINGL),y
	cmp	#$1F			; Check for last written value in SID
	beq	bank_is_sid

bank_is_unknown:
	lda	#BANK_UNK
	rts
	
bank_is_ram:
	lda	#BANK_RAM
	rts

bank_is_vic:
	lda	#BANK_VIC
	rts

bank_is_sid:
	lda	#BANK_SID
	rts

bank_is_mmu:
	lda	#BANK_MMU
	rts
	
bank_is_cfg:
	lda	#BANK_CFG
	rts
	
	
	
bank_type:
	.byte	" RAM VIC SID CFG MMU ???"
	
	;     00        01        02        04        08        10        20        40        80
	;               bit 0     bit 1     bit 2     bit 3     bit 4     bit 5     bit 6     bit 7
bank_d000:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d040:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_UNK, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d080:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_VIC, BANK_MMU, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d0c0:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG
bank_d100:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d200:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d300:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
bank_d400:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
bank_d500:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
bank_d600:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
bank_d700:
	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_RAM, BANK_SID, BANK_SID
	
test_turbo_io:
	lda	#42
	sta	CFGENA

	; Turbo on
	lda	#$80
	sta	CFGTUR
	
	; Test colorRAM access
	ldx	#$00
test_turbo_io_1:
	lda	COLORRAM,x
	sta	color_copy,x
	txa
	sta	COLORRAM,x
	inx
	bne	test_turbo_io_1

test_turbo_io_2:
	lda	COLORRAM,x
	and	#$0F
	sta	CMP_TEMP
	txa
	and	#$0F
	cmp	CMP_TEMP
	bne	test_turbo_io_fail
	lda	color_copy,x
	sta	COLORRAM,x
	inx
	bne	test_turbo_io_2
	; Test ok
	lda	#$D8
	cmp #$D8
	jsr	redgreen_hex

	; Turbo off
	lda	#$00
	sta	CFGTUR
	rts
	
test_turbo_io_fail:
	lda	#$D8
	jsr	redgreen_hex

	; Turbo off
	lda	#$00
	sta	CFGTUR
	rts

	

	
color_copy:
	.repeat	256
	.byte	0
	.endrep
	
	
test_turbo:	
	STRING test_turbo_str

	; Enter configuration mode for this test
	lda	#42
	sta	CFGENA

	lda	#0
	sta	turbo_idx
	sta	CFGTUR

	; Turbo is off and every option disabled
	; Turbo bit must be invisible at D030 and not influence the turbo functionality
	;
	lda	$D030
	cmp	#$ff
	jsr	redgreen_hex

	lda	#$00
	sta	$D030
	lda	$D030
	cmp	#$ff
	jsr	redgreen_hex
	lda	CFGTUR
	cmp	#$00
	jsr	redgreen_hex
;	jsr	test_show_turbo
	
	lda	#$01
	sta	$D030
	lda	$D030
	cmp	#$ff
	jsr	redgreen_hex
	lda	CFGTUR
	cmp	#$00
	jsr	redgreen_hex
;	jsr	test_show_turbo
	
	; Enable turbo bit at D030
	; Turbo bit must be visible at D030 and allow control of the turbo
	;
	jsr	space
	lda	#$20
	sta	CFGTUR

	lda	$D030
	cmp	#$fe
	jsr	redgreen_hex

	lda	#$01
	sta	$D030
	lda	$D030
	cmp	#$ff
	jsr	redgreen_hex
	lda	CFGTUR
	cmp	#$A0
	jsr	redgreen_hex
;	jsr	test_show_turbo

	lda	#$00
	sta	$D030
	lda	$D030
	cmp	#$fe
	jsr	redgreen_hex
	lda	CFGTUR
	cmp	#$20
	jsr	redgreen_hex

	SPACES 1
	jsr	test_turbo_io
	
	; Test all the available speed options of the turbo
	;
	SPACES 3

	; 1x speed
	lda	#$00
	sta	CFGTUR
	jsr	test_show_turbo
	; 2x speed
	lda	#$82
	sta	CFGTUR
	jsr	test_show_turbo
	; 3x speed
	lda	#$83
	sta	CFGTUR
	jsr	test_show_turbo
	; 4x speed
	lda	#$84
	sta	CFGTUR
	jsr	test_show_turbo
	; 5x speed
	lda	#$85
	sta	CFGTUR
	jsr	test_show_turbo
	; 6x speed
	lda	#$86
	sta	CFGTUR
	jsr	test_show_turbo
	; Unlimited speed
	lda	#$80
	sta	CFGTUR
	jsr	test_show_turbo
	SPACES 5
	
	; 25% speed
	lda	#$8F
	sta	CFGTUR
	jsr	test_show_turbo
	; 50% speed
	lda	#$8E
	sta	CFGTUR
	jsr	test_show_turbo
	; 75% speed
	lda	#$8D
	sta	CFGTUR
	jsr	test_show_turbo
	; 100% speed
	lda	#$8C
	sta	CFGTUR
	jsr	test_show_turbo

	SPACES 21
	; Turbo off
	lda	#$00
	sta	CFGTUR
	rts
	

test_show_turbo:
	jsr	space
	
	; Copy turbo routine to 0300 to always have the same fixed position.
	; As the test code can change alignment issues can influence the test results
	ldx	#$00
test_show_turbo1:
	lda	test_turbo_speed,x
	sta	$0300,x
	inx
	bne test_show_turbo1
	
	jsr	$0300
	tya
	ldy	turbo_idx
	cmp	turbo_cmp,y
	jsr	redgreen_hex
	inc	turbo_idx
	txa
	jmp	printhex

test_turbo_speed:
	ldx	#$00
	ldy	#$00
test_turbo_speed1:
	lda	RASTER
	cmp	#$F1
	bne	test_turbo_speed1
	
test_turbo_speed2:
	lda	RASTER
	cmp	#$F0
	beq	test_turbo_speed_end
	nop
	inx
	bne	test_turbo_speed2
	iny
	bne	test_turbo_speed2
test_turbo_speed_end:
	rts

turbo_idx:
	.byte	0
	; bigger numbers mean faster, these are in line with beta 9d
turbo_cmp:
	.byte	$04, $0f, $14, $19, $1e, $24, $24   ; no,2x,3x,4x,5x,6x,unlim
	.byte	$01, $02, $03, $04                  ; 25,50,75,100 percent

test_clkspeed:
	STRING	test_clkspeed_str
	SPACES	7
	
	lda	#$04
	sta	REPEATCNT
	
test_clkspeed_again:
	lda	#$FF
	sta	CIA1_TALO
	sta	CIA1_TAHI
	sta	CIA1_TBLO
	sta	CIA1_TBHI
	lda	#$90
	sta	CIA1_CRA
	; Counter B counts counter A underflows
	; Access TOD clock registers
	lda	#$51			
	sta	CIA1_CRB

	; Start TOD
	lda	#$00
	sta	CIA1_TODTEN
	lda	CIA1_TODTEN
	
	ldx	#$91
	ldy	#$80
	lda	CIA1_TODSEC
test_clkspeed1:
	cmp	CIA1_TODSEC		; Check for TOD seconds change
	beq	test_clkspeed1
	stx	CIA1_CRA		; Start timer
	lda	CIA1_TODSEC
test_clkspeed2:
	cmp	CIA1_TODSEC		; Check for TOD seconds change
	beq	test_clkspeed2
	sty	CIA1_CRA		; Stop timer
	
	lda	CIA1_TBHI
	jsr	printhex
	lda	CIA1_TBLO
	jsr	printhex
	lda	CIA1_TAHI
	jsr	printhex
	lda	CIA1_TALO
	jsr	printhex
	SPACES	2
	
	dec	REPEATCNT
	bne	test_clkspeed_again
	rts

	
coreid_str:
	.byte   "CoreID: ", 0
version_str:
	.byte   "  Version: '", 0
startup_str:
	.byte	"Startup CFGENA=", 0
startup_cfgtur_str:
	.byte	",CFGTUR=", 0
startup_cfgreg_str:
	.byte	",CFGREG=", 0
test_cfgena_str:
	.byte	"Test CFGENA: ", 0
test_cfgreg_str:
	.byte	"Test CFGREG: ", 0
test_turbo_str:
	.byte	"Test Turbo: ", 0
test_clkspeed_str:
	.byte	"Test Clock Speed (timer vs TOD): ", 0
done_str:
	.byte	"Test done (space to test again)", 0
hextbl:
	.byte	"0123456789ABCDEF"

clear_screen:
	ldx	#$00
clear_screen1:
	lda	#$20
	sta	REGENPOS,x
	sta	REGENPOS+$0100,x
	sta	REGENPOS+$0200,x
	sta	REGENPOS+$0300,x
	lda	COLOR
	sta	COLORRAM,x
	sta	COLORRAM+$0100,x
	sta	COLORRAM+$0200,x
	sta	COLORRAM+$0300,x
	inx
	bne	clear_screen1
	
	lda	#<REGENPOS
	sta CURSORL
	lda	#>REGENPOS
	sta CURSORH
	lda	#<COLORRAM
	sta COLORL
	lda	#>COLORRAM
	sta COLORH
	rts

backup_storage:
	.repeat	256
	.byte	0
	.endrep

backup_d700:
	; Enable all Chameleon registers
	lda	#$ff
	sta	CFGREG

	ldx #$00
backup_d700_l:
	lda $D700,x
	sta backup_storage,x
	inx
	bne backup_d700_l
	rts

restore_d700:
	; Enable all Chameleon registers
	lda	#$ff
	sta	CFGREG

	ldx #$00
restore_d700_l:
	lda backup_storage,x
	sta $D700,x
	inx
	bne restore_d700_l
	rts


printstr:
	stx	STRINGL
	sty	STRINGH
	ldy	#$00
printstr1:
	lda	(STRINGL),y
	beq	printstr_e
	jsr	print_char
	inc	STRINGL
	bne	printstr1
	inc	STRINGH
	bne	printstr1
printstr_e:
	rts
	
printhex:
	pha
	lsr
	lsr
	lsr
	lsr
	jsr	printnibble
	pla
printnibble:
	and	#$0f
	stx	print_tempx
	tax
	lda	hextbl,x
	ldx	print_tempx
	jmp	print_char
print_tempx:
	.byte	0

redgreen:
	pha
	beq	redgreen2
	lda	#RED_COLOR
redgreen1:
	sta	COLOR
	pla
	rts
redgreen2:	
	lda	#GRN_COLOR
	bne	redgreen1
redgreen_hex:
	jsr	redgreen
	jsr	printhex
	lda	#DEF_COLOR
	sta	COLOR
	rts
	
print_spaces:
	jsr	space
	dex
	bne	print_spaces
	rts
space:
	lda	#$20
print_char:
	sty	print_tempy
	ldy	#$00
	sta	(CURSORL),y
	lda	COLOR
	sta	(COLORL),y
	inc	CURSORL
	inc	COLORL
	bne	print_char_e
	inc	CURSORH
	inc	COLORH
print_char_e:
	ldy	print_tempy
	rts
print_tempy:
	.byte	0