ca65 V2.12.0 - (C) Copyright 1998-2005 Ullrich von Bassewitz
Main file   : chameleon_test.asm
Current file: chameleon_test.asm

000000r 1               
000000r 1               	.include "basicloader.asm"
000000r 2               	.code
000000r 2               
000000r 2  rr rr        	.word	basicLoader
000002r 2               basicLoader:
000002r 2               	; 2014 SYS(2080):PW.SOFT.
000002r 2  16 08 DE 07  	.byte	$16, $08, $de, $07, $9e, $28, $32, $30
000006r 2  9E 28 32 30  
00000Ar 2  38 30 29 3A  	.byte	$38, $30, $29, $3a, $50, $57, $2E, $53
00000Er 2  50 57 2E 53  
000012r 2  4F 46 54 2E  	.byte	$4F, $46, $54, $2E, $00, $00, $00, $00
000016r 2  00 00 00 00  
00001Ar 2  00 00 00 00  	.byte	$00, $00, $00, $00, $00, $00, $00
00001Er 2  00 00 00     
000021r 2               
000021r 1               	.include "chameleon_test_chars.asm"
000021r 2               	.segment "DATA3800"
000000r 2               
000000r 2  00 00 00 00  	.repeat (32*8)
000004r 2  00 00 00 00  
000008r 2  00 00 00 00  
000100r 2               	.byte $00
000100r 2               	.endrep
000100r 2               
000100r 2               characters:
000100r 2  00 00 00 00  	.byte	$00, $00, $00, $00, $00, $00, $00, $00
000104r 2  00 00 00 00  
000108r 2  18 18 18 18  	.byte	$18, $18, $18, $18, $00, $00, $18, $00    ; 33  !
00010Cr 2  00 00 18 00  
000110r 2  66 66 66 00  	.byte	$66, $66, $66, $00, $00, $00, $00, $00
000114r 2  00 00 00 00  
000118r 2  66 66 FF 66  	.byte	$66, $66, $FF, $66, $FF, $66, $66, $00
00011Cr 2  FF 66 66 00  
000120r 2  18 3E 60 3C  	.byte	$18, $3E, $60, $3C, $06, $7C, $18, $00
000124r 2  06 7C 18 00  
000128r 2  62 66 0C 18  	.byte	$62, $66, $0C, $18, $30, $66, $46, $00
00012Cr 2  30 66 46 00  
000130r 2  3C 66 3C 38  	.byte	$3C, $66, $3C, $38, $67, $66, $3F, $00
000134r 2  67 66 3F 00  
000138r 2  06 0C 18 00  	.byte	$06, $0C, $18, $00, $00, $00, $00, $00
00013Cr 2  00 00 00 00  
000140r 2  0C 18 30 30  	.byte	$0C, $18, $30, $30, $30, $18, $0C, $00
000144r 2  30 18 0C 00  
000148r 2  30 18 0C 0C  	.byte	$30, $18, $0C, $0C, $0C, $18, $30, $00
00014Cr 2  0C 18 30 00  
000150r 2  00 66 3C FF  	.byte	$00, $66, $3C, $FF, $3C, $66, $00, $00
000154r 2  3C 66 00 00  
000158r 2  00 18 18 7E  	.byte	$00, $18, $18, $7E, $18, $18, $00, $00
00015Cr 2  18 18 00 00  
000160r 2  00 00 00 00  	.byte	$00, $00, $00, $00, $00, $18, $18, $30
000164r 2  00 18 18 30  
000168r 2  00 00 00 7E  	.byte	$00, $00, $00, $7E, $00, $00, $00, $00
00016Cr 2  00 00 00 00  
000170r 2  00 00 00 00  	.byte	$00, $00, $00, $00, $00, $18, $18, $00
000174r 2  00 18 18 00  
000178r 2  00 03 06 0C  	.byte	$00, $03, $06, $0C, $18, $30, $60, $00
00017Cr 2  18 30 60 00  
000180r 2  3C 66 6E 76  	.byte	$3C, $66, $6E, $76, $66, $66, $3C, $00
000184r 2  66 66 3C 00  
000188r 2  18 18 38 18  	.byte	$18, $18, $38, $18, $18, $18, $7E, $00
00018Cr 2  18 18 7E 00  
000190r 2  3C 66 06 0C  	.byte	$3C, $66, $06, $0C, $30, $60, $7E, $00
000194r 2  30 60 7E 00  
000198r 2  3C 66 06 1C  	.byte	$3C, $66, $06, $1C, $06, $66, $3C, $00
00019Cr 2  06 66 3C 00  
0001A0r 2  06 0E 1E 66  	.byte	$06, $0E, $1E, $66, $7F, $06, $06, $00
0001A4r 2  7F 06 06 00  
0001A8r 2  7E 60 7C 06  	.byte	$7E, $60, $7C, $06, $06, $66, $3C, $00
0001ACr 2  06 66 3C 00  
0001B0r 2  3C 66 60 7C  	.byte	$3C, $66, $60, $7C, $66, $66, $3C, $00
0001B4r 2  66 66 3C 00  
0001B8r 2  7E 66 0C 18  	.byte	$7E, $66, $0C, $18, $18, $18, $18, $00
0001BCr 2  18 18 18 00  
0001C0r 2  3C 66 66 3C  	.byte	$3C, $66, $66, $3C, $66, $66, $3C, $00
0001C4r 2  66 66 3C 00  
0001C8r 2  3C 66 66 3E  	.byte	$3C, $66, $66, $3E, $06, $66, $3C, $00
0001CCr 2  06 66 3C 00  
0001D0r 2  00 00 18 00  	.byte	$00, $00, $18, $00, $00, $18, $00, $00
0001D4r 2  00 18 00 00  
0001D8r 2  00 00 18 00  	.byte	$00, $00, $18, $00, $00, $18, $18, $30
0001DCr 2  00 18 18 30  
0001E0r 2  0E 18 30 60  	.byte	$0E, $18, $30, $60, $30, $18, $0E, $00
0001E4r 2  30 18 0E 00  
0001E8r 2  00 00 7E 00  	.byte	$00, $00, $7E, $00, $7E, $00, $00, $00
0001ECr 2  7E 00 00 00  
0001F0r 2  70 18 0C 06  	.byte	$70, $18, $0C, $06, $0C, $18, $70, $00
0001F4r 2  0C 18 70 00  
0001F8r 2  3C 66 06 0C  	.byte	$3C, $66, $06, $0C, $18, $00, $18, $00
0001FCr 2  18 00 18 00  
000200r 2               
000200r 2               	; Uppercase
000200r 2  1C 22 2E 2A  	.byte	$1C, $22, $2E, $2A, $2E, $20, $1C, $00   ; @
000204r 2  2E 20 1C 00  
000208r 2  18 3C 66 7E  	.byte	$18, $3C, $66, $7E, $66, $66, $66, $00   ; A
00020Cr 2  66 66 66 00  
000210r 2  7C 66 66 7C  	.byte	$7C, $66, $66, $7C, $66, $66, $7C, $00   ; B
000214r 2  66 66 7C 00  
000218r 2  3C 66 60 60  	.byte	$3C, $66, $60, $60, $60, $66, $3C, $00   ; C
00021Cr 2  60 66 3C 00  
000220r 2  78 6C 66 66  	.byte	$78, $6C, $66, $66, $66, $6C, $78, $00   ; D
000224r 2  66 6C 78 00  
000228r 2  7E 60 60 78  	.byte	$7E, $60, $60, $78, $60, $60, $7E, $00   ; E
00022Cr 2  60 60 7E 00  
000230r 2  7E 60 60 78  	.byte	$7E, $60, $60, $78, $60, $60, $60, $00   ; F
000234r 2  60 60 60 00  
000238r 2  3C 66 60 6E  	.byte	$3C, $66, $60, $6E, $66, $66, $3C, $00   ; G
00023Cr 2  66 66 3C 00  
000240r 2  66 66 66 7E  	.byte	$66, $66, $66, $7E, $66, $66, $66, $00   ; H
000244r 2  66 66 66 00  
000248r 2  3C 18 18 18  	.byte	$3C, $18, $18, $18, $18, $18, $3C, $00   ; I
00024Cr 2  18 18 3C 00  
000250r 2  1E 0C 0C 0C  	.byte	$1E, $0C, $0C, $0C, $0C, $6C, $38, $00   ; J
000254r 2  0C 6C 38 00  
000258r 2  66 6C 78 70  	.byte	$66, $6C, $78, $70, $78, $6C, $66, $00   ; K
00025Cr 2  78 6C 66 00  
000260r 2  60 60 60 60  	.byte	$60, $60, $60, $60, $60, $60, $7E, $00   ; L
000264r 2  60 60 7E 00  
000268r 2  63 77 7F 6B  	.byte	$63, $77, $7F, $6B, $63, $63, $63, $00   ; M
00026Cr 2  63 63 63 00  
000270r 2  66 76 7E 7E  	.byte	$66, $76, $7E, $7E, $6E, $66, $66, $00   ; N
000274r 2  6E 66 66 00  
000278r 2  3C 66 66 66  	.byte	$3C, $66, $66, $66, $66, $66, $3C, $00   ; O
00027Cr 2  66 66 3C 00  
000280r 2  7C 66 66 7C  	.byte	$7C, $66, $66, $7C, $60, $60, $60, $00   ; P
000284r 2  60 60 60 00  
000288r 2  3C 66 66 66  	.byte	$3C, $66, $66, $66, $66, $3C, $0E, $00   ; Q
00028Cr 2  66 3C 0E 00  
000290r 2  7C 66 66 7C  	.byte	$7C, $66, $66, $7C, $78, $6C, $66, $00   ; R
000294r 2  78 6C 66 00  
000298r 2  3C 66 60 3C  	.byte	$3C, $66, $60, $3C, $06, $66, $3C, $00   ; S
00029Cr 2  06 66 3C 00  
0002A0r 2  7E 18 18 18  	.byte	$7E, $18, $18, $18, $18, $18, $18, $00   ; T
0002A4r 2  18 18 18 00  
0002A8r 2  66 66 66 66  	.byte	$66, $66, $66, $66, $66, $66, $3C, $00   ; U
0002ACr 2  66 66 3C 00  
0002B0r 2  66 66 66 66  	.byte	$66, $66, $66, $66, $66, $3C, $18, $00   ; V
0002B4r 2  66 3C 18 00  
0002B8r 2  63 63 63 6B  	.byte	$63, $63, $63, $6B, $7F, $77, $63, $00   ; W
0002BCr 2  7F 77 63 00  
0002C0r 2  66 66 3C 18  	.byte	$66, $66, $3C, $18, $3C, $66, $66, $00   ; X
0002C4r 2  3C 66 66 00  
0002C8r 2  66 66 66 3C  	.byte	$66, $66, $66, $3C, $18, $18, $18, $00   ; Y
0002CCr 2  18 18 18 00  
0002D0r 2  7E 06 0C 18  	.byte	$7E, $06, $0C, $18, $30, $60, $7E, $00   ; Z
0002D4r 2  30 60 7E 00  
0002D8r 2  1C 10 10 10  	.byte	$1C, $10, $10, $10, $10, $10, $1C, $00   ; [
0002DCr 2  10 10 1C 00  
0002E0r 2  40 20 10 08  	.byte	$40, $20, $10, $08, $04, $02, $01, $00   ; \
0002E4r 2  04 02 01 00  
0002E8r 2  1C 04 04 04  	.byte	$1C, $04, $04, $04, $04, $04, $1C, $00   ; ]
0002ECr 2  04 04 1C 00  
0002F0r 2  08 14 22 00  	.byte	$08, $14, $22, $00, $00, $00, $00, $00   ; ^
0002F4r 2  00 00 00 00  
0002F8r 2  00 00 00 00  	.byte	$00, $00, $00, $00, $00, $00, $00, $7F   ; _
0002FCr 2  00 00 00 7F  
000300r 2               	; Lower case
000300r 2  10 08 00 00  	.byte	$10, $08, $00, $00, $00, $00, $00, $00   ; `
000304r 2  00 00 00 00  
000308r 2  00 00 3C 06  	.byte	$00, $00, $3C, $06, $3E, $66, $3E, $00
00030Cr 2  3E 66 3E 00  
000310r 2  00 60 60 7C  	.byte	$00, $60, $60, $7C, $66, $66, $7C, $00
000314r 2  66 66 7C 00  
000318r 2  00 00 3C 60  	.byte	$00, $00, $3C, $60, $60, $60, $3C, $00
00031Cr 2  60 60 3C 00  
000320r 2  00 06 06 3E  	.byte	$00, $06, $06, $3E, $66, $66, $3E, $00
000324r 2  66 66 3E 00  
000328r 2  00 00 3C 66  	.byte	$00, $00, $3C, $66, $7E, $60, $3C, $00
00032Cr 2  7E 60 3C 00  
000330r 2  00 0E 18 3E  	.byte	$00, $0E, $18, $3E, $18, $18, $18, $00
000334r 2  18 18 18 00  
000338r 2  00 00 3E 66  	.byte	$00, $00, $3E, $66, $66, $3E, $06, $7C
00033Cr 2  66 3E 06 7C  
000340r 2  00 60 60 7C  	.byte	$00, $60, $60, $7C, $66, $66, $66, $00
000344r 2  66 66 66 00  
000348r 2  00 18 00 38  	.byte	$00, $18, $00, $38, $18, $18, $3C, $00
00034Cr 2  18 18 3C 00  
000350r 2  00 06 00 06  	.byte	$00, $06, $00, $06, $06, $06, $06, $3C
000354r 2  06 06 06 3C  
000358r 2  00 60 60 6C  	.byte	$00, $60, $60, $6C, $78, $6C, $66, $00
00035Cr 2  78 6C 66 00  
000360r 2  00 38 18 18  	.byte	$00, $38, $18, $18, $18, $18, $3C, $00
000364r 2  18 18 3C 00  
000368r 2  00 00 66 7F  	.byte	$00, $00, $66, $7F, $7F, $6B, $63, $00
00036Cr 2  7F 6B 63 00  
000370r 2  00 00 7C 66  	.byte	$00, $00, $7C, $66, $66, $66, $66, $00
000374r 2  66 66 66 00  
000378r 2  00 00 3C 66  	.byte	$00, $00, $3C, $66, $66, $66, $3C, $00
00037Cr 2  66 66 3C 00  
000380r 2  00 00 7C 66  	.byte	$00, $00, $7C, $66, $66, $7C, $60, $60
000384r 2  66 7C 60 60  
000388r 2  00 00 3E 66  	.byte	$00, $00, $3E, $66, $66, $3E, $06, $06
00038Cr 2  66 3E 06 06  
000390r 2  00 00 7C 66  	.byte	$00, $00, $7C, $66, $60, $60, $60, $00
000394r 2  60 60 60 00  
000398r 2  00 00 3E 60  	.byte	$00, $00, $3E, $60, $3C, $06, $7C, $00
00039Cr 2  3C 06 7C 00  
0003A0r 2  00 18 7E 18  	.byte	$00, $18, $7E, $18, $18, $18, $0E, $00
0003A4r 2  18 18 0E 00  
0003A8r 2  00 00 66 66  	.byte	$00, $00, $66, $66, $66, $66, $3E, $00
0003ACr 2  66 66 3E 00  
0003B0r 2  00 00 66 66  	.byte	$00, $00, $66, $66, $66, $3C, $18, $00
0003B4r 2  66 3C 18 00  
0003B8r 2  00 00 63 6B  	.byte	$00, $00, $63, $6B, $7F, $3E, $36, $00
0003BCr 2  7F 3E 36 00  
0003C0r 2  00 00 66 3C  	.byte	$00, $00, $66, $3C, $18, $3C, $66, $00
0003C4r 2  18 3C 66 00  
0003C8r 2  00 00 66 66  	.byte	$00, $00, $66, $66, $66, $3E, $0C, $78
0003CCr 2  66 3E 0C 78  
0003D0r 2  00 00 7E 0C  	.byte	$00, $00, $7E, $0C, $18, $30, $7E, $00
0003D4r 2  18 30 7E 00  
0003D8r 2  0C 10 10 20  	.byte	$0C, $10, $10, $20, $10, $10, $0C, $00   ; {
0003DCr 2  10 10 0C 00  
0003E0r 2  08 08 08 08  	.byte	$08, $08, $08, $08, $08, $08, $08, $00   ; |
0003E4r 2  08 08 08 00  
0003E8r 2  30 08 08 04  	.byte	$30, $08, $08, $04, $08, $08, $30, $00   ; }
0003ECr 2  08 08 30 00  
0003F0r 2  00 00 30 49  	.byte	$00, $00, $30, $49, $06, $00, $00, $00   ; ~
0003F4r 2  06 00 00 00  
0003F8r 2  FF FF FF FF  	.byte	$FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF    ; $7F  127  Solid block
0003FCr 2  FF FF FF FF  
000400r 2               ;	.byte	$00, $00, $00, $00, $00, $00, $00, $00
000400r 2               
000400r 1               	.code
000021r 1  4C rr rr     	jmp main
000024r 1               
000024r 1               COREID    = $04
000024r 1               ORGCFGENA = $10     ; Startup value of CFGENA
000024r 1               ORGCFGTUR = $11     ; Startup value of CFGTUR
000024r 1               ORGCFGREG = $12     ; Startup value of CFGREG
000024r 1               STRINGL   = $f9
000024r 1               STRINGH   = $fa
000024r 1               COLOR     = $fb
000024r 1               COLORL    = $fc
000024r 1               COLORH    = $fd
000024r 1               CURSORL   = $fe
000024r 1               CURSORH   = $ff
000024r 1               REGENPOS  = $0400
000024r 1               CHARPOS   = $3800
000024r 1               RASTER    = $D012
000024r 1               VIC_VMCB  = $D018
000024r 1               VERIDX    = $D0A8
000024r 1               VERDAT    = $D0A9
000024r 1               CFGTUR    = $D0F3
000024r 1               CFGREG    = $D0FA
000024r 1               CFGDIS    = $D0FD
000024r 1               CFGENA    = $D0FE
000024r 1               CFGRTI    = $D0FF
000024r 1               COLORRAM  = $D800
000024r 1               
000024r 1               BANK_RAM = 0
000024r 1               BANK_VIC = 1
000024r 1               BANK_SID = 2
000024r 1               BANK_CFG = 3
000024r 1               BANK_MMU = 4
000024r 1               BANK_UNK = 5
000024r 1               
000024r 1               DEF_COLOR = 14
000024r 1               GRN_COLOR = 5
000024r 1               RED_COLOR = 2
000024r 1               
000024r 1               	.macro SPACES nr
000024r 1               	ldx	#nr
000024r 1               	jsr	print_spaces
000024r 1               	.endmacro
000024r 1               
000024r 1               	.macro STRING addr
000024r 1               		ldx	#<addr
000024r 1               		ldy #>addr
000024r 1               		jsr	printstr
000024r 1               	.endmacro
000024r 1               
000024r 1               	.macro	BANK_RESULT bank_a, print_a
000024r 1               	ldx	#<bank_a
000024r 1               	ldy	#>bank_a
000024r 1               	lda	#>print_a
000024r 1               	jsr	printhex
000024r 1               	lda	#<print_a
000024r 1               	jsr	printhex
000024r 1               	jsr	bank_result_line
000024r 1               	.endmacro
000024r 1               
000024r 1               main:
000024r 1               	; Don't want interrupts when banking etc.
000024r 1  78           	sei
000025r 1               
000025r 1  AD FE D0     	lda	CFGENA
000028r 1  85 10        	sta	ORGCFGENA
00002Ar 1               
00002Ar 1               	; Set position of regen-buffer and character definitions
00002Ar 1  A9 1E        	lda	#(REGENPOS/1024)*16 + (CHARPOS/1024)
00002Cr 1  8D 18 D0     	sta	VIC_VMCB
00002Fr 1               
00002Fr 1  A9 0E        	lda	#DEF_COLOR
000031r 1  85 FB        	sta	COLOR
000033r 1               
000033r 1  20 rr rr     	jsr	clear_screen
000036r 1               
000036r 1  A9 2A        	lda	#42
000038r 1  8D FE D0     	sta	CFGENA
00003Br 1  AD F3 D0     	lda	CFGTUR
00003Er 1  85 11        	sta ORGCFGTUR
000040r 1  AD FA D0     	lda	CFGREG
000043r 1  85 12        	sta ORGCFGREG
000045r 1               
000045r 1               	; Enable all Chameleon registers
000045r 1  A9 FF        	lda	#$ff
000047r 1  8D FA D0     	sta	CFGREG
00004Ar 1               
00004Ar 1  20 rr rr     	jsr	show_coreid
00004Dr 1  20 rr rr     	jsr	show_version
000050r 1  20 rr rr     	jsr	show_startup_values
000053r 1  20 rr rr     	jsr	test_cfgena
000056r 1               
000056r 1  A2 28 20 rr  	SPACES 40
00005Ar 1  rr           
00005Br 1  20 rr rr     	jsr	test_cfgreg
00005Er 1  A2 28 20 rr  	SPACES 40
000062r 1  rr           
000063r 1  20 rr rr     	jsr	test_turbo
000066r 1               
000066r 1               
000066r 1               
000066r 1               	; Banking test
000066r 1               	;
000066r 1               
000066r 1               
000066r 1               
000066r 1               loop1:
000066r 1  4C rr rr     	jmp	loop1
000069r 1               
000069r 1               	; Show coreID number
000069r 1               	;
000069r 1               show_coreid:
000069r 1  A2 rr A0 rr  	STRING coreid_str
00006Dr 1  20 rr rr     
000070r 1  AD FE D0     	lda	CFGENA
000073r 1  85 04        	sta	COREID
000075r 1  4C rr rr     	jmp	printhex
000078r 1               
000078r 1               	; Show core version number
000078r 1               	;
000078r 1               show_version:
000078r 1  A2 rr A0 rr  	STRING version_str
00007Cr 1  20 rr rr     
00007Fr 1  A2 00        	ldx	#0
000081r 1               corever1:
000081r 1  8E A8 D0     	stx	VERIDX
000084r 1  AD A9 D0     	lda	VERDAT
000087r 1  20 rr rr     	jsr	print_char
00008Ar 1  E8           	inx
00008Br 1  E0 10        	cpx	#16
00008Dr 1  D0 F2        	bne	corever1
00008Fr 1  A9 27        	lda	#39
000091r 1  20 rr rr     	jsr	print_char
000094r 1  4C rr rr     	jmp space
000097r 1               
000097r 1               test_cfgena:
000097r 1  A2 rr A0 rr  	STRING test_cfgena_str
00009Br 1  20 rr rr     
00009Er 1               
00009Er 1               	; Disable configuration registers by writing to CFGENA
00009Er 1  A9 FF        	lda	#$ff
0000A0r 1  8D FE D0     	sta	CFGENA
0000A3r 1  AD FE D0     	lda	CFGENA
0000A6r 1  C9 FF        	cmp	#$ff
0000A8r 1  20 rr rr     	jsr	redgreen_hex
0000ABr 1  20 rr rr     	jsr	space
0000AEr 1               
0000AEr 1               	; Check influence read/write of CFGRTI on configuration mode
0000AEr 1  A9 2A        	lda	#42
0000B0r 1  8D FE D0     	sta	CFGENA
0000B3r 1  AD FF D0     	lda	CFGRTI			; load should not disable config mode
0000B6r 1  C9 40        	cmp	#$40
0000B8r 1  20 rr rr     	jsr	redgreen_hex
0000BBr 1  AD FE D0     	lda	CFGENA
0000BEr 1  C5 04        	cmp	COREID
0000C0r 1  20 rr rr     	jsr	redgreen_hex
0000C3r 1  8D FF D0     	sta	CFGRTI			; store should disable config mode
0000C6r 1  AD FE D0     	lda	CFGENA
0000C9r 1  C9 FF        	cmp	#$FF
0000CBr 1  20 rr rr     	jsr	redgreen_hex
0000CEr 1  AD FD D0     	lda	CFGDIS
0000D1r 1  C9 FF        	cmp	#$FF
0000D3r 1  20 rr rr     	jsr	redgreen_hex
0000D6r 1  AD FF D0     	lda	CFGRTI
0000D9r 1  C9 FF        	cmp	#$FF
0000DBr 1  20 rr rr     	jsr	redgreen_hex
0000DEr 1  20 rr rr     	jsr	space
0000E1r 1               
0000E1r 1               	; Check influence read/write of CFGDIS on configuration mode
0000E1r 1  A9 2A        	lda	#42
0000E3r 1  8D FE D0     	sta	CFGENA
0000E6r 1  AD FD D0     	lda	CFGDIS			; load should not disable config mode
0000E9r 1  20 rr rr     	jsr	printhex
0000ECr 1  AD FE D0     	lda	CFGENA
0000EFr 1  C5 04        	cmp	COREID
0000F1r 1  20 rr rr     	jsr	redgreen_hex
0000F4r 1  8D FD D0     	sta	CFGDIS			; store should disable config mode
0000F7r 1  AD FE D0     	lda	CFGENA
0000FAr 1  C9 FF        	cmp	#$FF
0000FCr 1  20 rr rr     	jsr	redgreen_hex
0000FFr 1  AD FD D0     	lda	CFGDIS
000102r 1  C9 FF        	cmp	#$FF
000104r 1  20 rr rr     	jsr	redgreen_hex
000107r 1  AD FF D0     	lda	CFGRTI
00010Ar 1  C9 FF        	cmp	#$FF
00010Cr 1  20 rr rr     	jsr	redgreen_hex
00010Fr 1  A2 03 20 rr  	SPACES 3
000113r 1  rr           
000114r 1  60           	rts
000115r 1               
000115r 1               show_startup_values:
000115r 1  A2 rr A0 rr  	STRING startup_str
000119r 1  20 rr rr     
00011Cr 1  A5 10        	lda	ORGCFGENA
00011Er 1  20 rr rr     	jsr	printhex
000121r 1  A2 rr A0 rr  	STRING startup_cfgtur_str
000125r 1  20 rr rr     
000128r 1  A5 11        	lda	ORGCFGTUR
00012Ar 1  20 rr rr     	jsr	printhex
00012Dr 1  A2 rr A0 rr  	STRING startup_cfgreg_str
000131r 1  20 rr rr     
000134r 1  A5 12        	lda	ORGCFGREG
000136r 1  20 rr rr     	jsr	printhex
000139r 1  A2 03 20 rr  	SPACES 3
00013Dr 1  rr           
00013Er 1  60           	rts
00013Fr 1               
00013Fr 1               test_cfgreg:
00013Fr 1  A2 rr A0 rr  	STRING test_cfgreg_str
000143r 1  20 rr rr     
000146r 1  A2 1B 20 rr  	SPACES 27
00014Ar 1  rr           
00014Br 1               
00014Br 1               	; Enter configuration mode for this test
00014Br 1  A9 2A        	lda	#42
00014Dr 1  8D FE D0     	sta	CFGENA
000150r 1  A2 04 20 rr  	SPACES 4
000154r 1  rr           
000155r 1               
000155r 1  A9 80        	lda	#$80
000157r 1  A2 09        	ldx	#$09
000159r 1               test_cfgreg1:
000159r 1  CA           	dex
00015Ar 1  48           	pha
00015Br 1  48           	pha
00015Cr 1  48           	pha
00015Dr 1  8D FA D0     	sta	CFGREG
000160r 1  20 rr rr     	jsr space
000163r 1  20 rr rr     	jsr space
000166r 1  68           	pla
000167r 1  20 rr rr     	jsr	printhex
00016Ar 1  68           	pla
00016Br 1  20 rr rr     	jsr	bank_test
00016Er 1  68           	pla
00016Fr 1  4A           	lsr
000170r 1  E0 00        	cpx	#$00
000172r 1  D0 E5        	bne	test_cfgreg1
000174r 1               ;	jsr	space
000174r 1               
000174r 1  A2 rr A0 rr  	BANK_RESULT bank_d000, $d000
000178r 1  A9 D0 20 rr  
00017Cr 1  rr A9 00 20  
000185r 1  A2 rr A0 rr  	BANK_RESULT bank_d040, $d040
000189r 1  A9 D0 20 rr  
00018Dr 1  rr A9 40 20  
000196r 1  A2 rr A0 rr  	BANK_RESULT bank_d080, $d080
00019Ar 1  A9 D0 20 rr  
00019Er 1  rr A9 80 20  
0001A7r 1  A2 rr A0 rr  	BANK_RESULT bank_d0c0, $d0c0
0001ABr 1  A9 D0 20 rr  
0001AFr 1  rr A9 C0 20  
0001B8r 1  A2 rr A0 rr  	BANK_RESULT bank_d100, $d100
0001BCr 1  A9 D1 20 rr  
0001C0r 1  rr A9 00 20  
0001C9r 1  A2 rr A0 rr  	BANK_RESULT bank_d200, $d200
0001CDr 1  A9 D2 20 rr  
0001D1r 1  rr A9 00 20  
0001DAr 1  A2 rr A0 rr  	BANK_RESULT bank_d300, $d300
0001DEr 1  A9 D3 20 rr  
0001E2r 1  rr A9 00 20  
0001EBr 1  A2 rr A0 rr  	BANK_RESULT bank_d400, $d400
0001EFr 1  A9 D4 20 rr  
0001F3r 1  rr A9 00 20  
0001FCr 1  A2 rr A0 rr  	BANK_RESULT bank_d500, $d500
000200r 1  A9 D5 20 rr  
000204r 1  rr A9 00 20  
00020Dr 1  A2 rr A0 rr  	BANK_RESULT bank_d600, $d600
000211r 1  A9 D6 20 rr  
000215r 1  rr A9 00 20  
00021Er 1  A2 rr A0 rr  	BANK_RESULT bank_d700, $d700
000222r 1  A9 D7 20 rr  
000226r 1  rr A9 00 20  
00022Fr 1  60           	rts
000230r 1               
000230r 1               bank_result_line:
000230r 1  8E rr rr     	stx	bank_result_lda+1
000233r 1  8C rr rr     	sty	bank_result_lda+2
000236r 1  AD rr rr     	lda	bank_result_lda+1
000239r 1  18           	clc
00023Ar 1  69 09        	adc	#$09
00023Cr 1  8D rr rr     	sta	bank_result_cmp+1
00023Fr 1  AD rr rr     	lda	bank_result_lda+2
000242r 1  69 00        	adc	#$00
000244r 1  8D rr rr     	sta	bank_result_cmp+2
000247r 1               
000247r 1  A0 09        	ldy	#$09
000249r 1               bank_result_line1:
000249r 1  88           	dey
00024Ar 1  A2 05        	ldx	#GRN_COLOR
00024Cr 1  86 FB        	stx	COLOR
00024Er 1               bank_result_lda:
00024Er 1  B9 rr rr     	lda	bank_d000,y
000251r 1               bank_result_cmp:
000251r 1  D9 rr rr     	cmp	bank_d000,y
000254r 1  F0 04        	beq	bank_result_ok
000256r 1  A2 02        	ldx	#RED_COLOR
000258r 1  86 FB        	stx	COLOR
00025Ar 1               bank_result_ok:
00025Ar 1  18           	clc
00025Br 1  2A           	rol
00025Cr 1  2A           	rol
00025Dr 1  AA           	tax
00025Er 1  BD rr rr 20  	.repeat 4
000262r 1  rr rr E8 BD  
000266r 1  rr rr 20 rr  
00027Ar 1               	lda	bank_type,x
00027Ar 1               	jsr	print_char
00027Ar 1               	inx
00027Ar 1               	.endrep
00027Ar 1  A2 0E        	ldx	#DEF_COLOR
00027Cr 1  86 FB        	stx	COLOR
00027Er 1  C0 00        	cpy	#$00
000280r 1  D0 C7        	bne	bank_result_line1
000282r 1  60           	rts
000283r 1               
000283r 1               bank_test:
000283r 1  A9 00        	lda	#$00
000285r 1  85 F9        	sta	STRINGL
000287r 1  A9 D0        	lda	#$D0
000289r 1  85 FA        	sta	STRINGH
00028Br 1  20 rr rr     	jsr	bank_run_test
00028Er 1  9D rr rr     	sta	bank_d000,x
000291r 1  E6 FA        	inc	STRINGH
000293r 1  20 rr rr     	jsr	bank_run_test
000296r 1  9D rr rr     	sta	bank_d100,x
000299r 1  E6 FA        	inc	STRINGH
00029Br 1  20 rr rr     	jsr	bank_run_test
00029Er 1  9D rr rr     	sta	bank_d200,x
0002A1r 1  E6 FA        	inc	STRINGH
0002A3r 1  20 rr rr     	jsr	bank_run_test
0002A6r 1  9D rr rr     	sta	bank_d300,x
0002A9r 1  E6 FA        	inc	STRINGH
0002ABr 1  20 rr rr     	jsr	bank_run_test
0002AEr 1  9D rr rr     	sta	bank_d400,x
0002B1r 1  E6 FA        	inc	STRINGH
0002B3r 1  20 rr rr     	jsr	bank_run_test
0002B6r 1  9D rr rr     	sta	bank_d500,x
0002B9r 1  E6 FA        	inc	STRINGH
0002BBr 1  20 rr rr     	jsr	bank_run_test
0002BEr 1  9D rr rr     	sta	bank_d600,x
0002C1r 1  E6 FA        	inc	STRINGH
0002C3r 1  20 rr rr     	jsr	bank_run_test
0002C6r 1  9D rr rr     	sta	bank_d700,x
0002C9r 1               
0002C9r 1               	; For these addresses only run checks as writing will possibly currupt config registers.
0002C9r 1  A9 40        	lda	#$40
0002CBr 1  85 F9        	sta	STRINGL
0002CDr 1  A9 D0        	lda	#$D0
0002CFr 1  85 FA        	sta	STRINGH
0002D1r 1  20 rr rr     	jsr	bank_test_check
0002D4r 1  9D rr rr     	sta	bank_d040,x
0002D7r 1  A9 80        	lda	#$80
0002D9r 1  85 F9        	sta	STRINGL
0002DBr 1  20 rr rr     	jsr	bank_test_check
0002DEr 1  9D rr rr     	sta	bank_d080,x
0002E1r 1  A9 C0        	lda	#$C0
0002E3r 1  85 F9        	sta	STRINGL
0002E5r 1  20 rr rr     	jsr	bank_test_check
0002E8r 1  9D rr rr     	sta	bank_d0c0,x
0002EBr 1  60           	rts
0002ECr 1               
0002ECr 1               bank_run_test:
0002ECr 1  20 rr rr     	jsr	bank_test_pattern
0002EFr 1  4C rr rr     	jmp	bank_test_check
0002F2r 1               
0002F2r 1               bank_test_pattern:
0002F2r 1  A0 00        	ldy	#$00
0002F4r 1  A9 11        	lda	#$11
0002F6r 1  91 F9        	sta	(STRINGL),y
0002F8r 1  C8           	iny
0002F9r 1  A9 22        	lda	#$22
0002FBr 1  91 F9        	sta	(STRINGL),y
0002FDr 1  C8           	iny
0002FEr 1  A9 33        	lda	#$33
000300r 1  91 F9        	sta	(STRINGL),y
000302r 1  C8           	iny
000303r 1  A9 44        	lda	#$44
000305r 1  91 F9        	sta	(STRINGL),y
000307r 1               	; Write non-ascii code at offet 29. This is VERDAT register in D080-D0BF area
000307r 1               	; Can detect VIC vs RAM vs MMU. Should read back as F9 in VIC (color register), 29 when RAM and anything else when VERDAT.
000307r 1  A0 29        	ldy	#$29
000309r 1  A9 29        	lda	#$29
00030Br 1  91 F9        	sta	(STRINGL),y
00030Dr 1  A0 3E        	ldy	#$3E
00030Fr 1  A9 1F        	lda	#$1F
000311r 1  91 F9        	sta	(STRINGL),y
000313r 1  C8           	iny
000314r 1  91 F9        	sta	(STRINGL),y
000316r 1  60           	rts
000317r 1               
000317r 1               bank_test_check:
000317r 1  A0 00        	ldy	#$00
000319r 1  B1 F9        	lda	(STRINGL),y
00031Br 1  C9 1F        	cmp	#$1F			; Check for last written value in SID
00031Dr 1  F0 21        	beq	bank_check_sid
00031Fr 1  C8           	iny
000320r 1  B1 F9        	lda	(STRINGL),y
000322r 1  C9 22        	cmp	#$22
000324r 1  D0 21        	bne	bank_is_unknown
000326r 1  A0 29        	ldy	#$29
000328r 1  B1 F9        	lda	(STRINGL),y
00032Ar 1  C9 29        	cmp	#$29
00032Cr 1  F0 1C        	beq	bank_is_ram
00032Er 1  C9 F9        	cmp	#$F9
000330r 1  D0 21        	bne	bank_is_mmu
000332r 1  A0 3F        	ldy	#$3F
000334r 1  B1 F9        	lda	(STRINGL),y
000336r 1  C9 FF        	cmp	#$FF
000338r 1  F0 13        	beq	bank_is_vic
00033Ar 1  C9 40        	cmp	#$40			; Check for RTI on D0FF
00033Cr 1  F0 18        	beq	bank_is_cfg
00033Er 1  D0 07        	bne	bank_is_unknown
000340r 1               
000340r 1               bank_check_sid:
000340r 1  C8           	iny
000341r 1  B1 F9        	lda	(STRINGL),y
000343r 1  C9 1F        	cmp	#$1F			; Check for last written value in SID
000345r 1  F0 09        	beq	bank_is_sid
000347r 1               
000347r 1               bank_is_unknown:
000347r 1  A9 05        	lda	#BANK_UNK
000349r 1  60           	rts
00034Ar 1               
00034Ar 1               bank_is_ram:
00034Ar 1  A9 00        	lda	#BANK_RAM
00034Cr 1  60           	rts
00034Dr 1               
00034Dr 1               bank_is_vic:
00034Dr 1  A9 01        	lda	#BANK_VIC
00034Fr 1  60           	rts
000350r 1               
000350r 1               bank_is_sid:
000350r 1  A9 02        	lda	#BANK_SID
000352r 1  60           	rts
000353r 1               
000353r 1               bank_is_mmu:
000353r 1  A9 04        	lda	#BANK_MMU
000355r 1  60           	rts
000356r 1               
000356r 1               bank_is_cfg:
000356r 1  A9 03        	lda	#BANK_CFG
000358r 1  60           	rts
000359r 1               
000359r 1               
000359r 1               
000359r 1               bank_type:
000359r 1  20 52 41 4D  	.byte	" RAM VIC SID CFG MMU ???"
00035Dr 1  20 56 49 43  
000361r 1  20 53 49 44  
000371r 1               
000371r 1               	;     00        01        02        04        08        10        20        40        80
000371r 1               	;               bit 0     bit 1     bit 2     bit 3     bit 4     bit 5     bit 6     bit 7
000371r 1               bank_d000:
000371r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000375r 1  05 05 05 05  
000379r 1  05           
00037Ar 1  01 01 01 01  	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
00037Er 1  01 01 01 01  
000382r 1  01           
000383r 1               bank_d040:
000383r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000387r 1  05 05 05 05  
00038Br 1  05           
00038Cr 1  01 05 01 01  	.byte BANK_VIC, BANK_UNK, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
000390r 1  01 01 01 01  
000394r 1  01           
000395r 1               bank_d080:
000395r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000399r 1  05 05 05 05  
00039Dr 1  05           
00039Er 1  01 01 04 01  	.byte BANK_VIC, BANK_VIC, BANK_MMU, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
0003A2r 1  01 01 01 01  
0003A6r 1  01           
0003A7r 1               bank_d0c0:
0003A7r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
0003ABr 1  05 05 05 05  
0003AFr 1  05           
0003B0r 1  03 03 03 03  	.byte BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG, BANK_CFG
0003B4r 1  03 03 03 03  
0003B8r 1  03           
0003B9r 1               bank_d100:
0003B9r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
0003BDr 1  05 05 05 05  
0003C1r 1  05           
0003C2r 1  01 01 01 01  	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
0003C6r 1  00 01 01 01  
0003CAr 1  01           
0003CBr 1               bank_d200:
0003CBr 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
0003CFr 1  05 05 05 05  
0003D3r 1  05           
0003D4r 1  01 01 01 01  	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
0003D8r 1  00 01 01 01  
0003DCr 1  01           
0003DDr 1               bank_d300:
0003DDr 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
0003E1r 1  05 05 05 05  
0003E5r 1  05           
0003E6r 1  01 01 01 01  	.byte BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC, BANK_RAM, BANK_VIC, BANK_VIC, BANK_VIC, BANK_VIC
0003EAr 1  00 01 01 01  
0003EEr 1  01           
0003EFr 1               bank_d400:
0003EFr 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
0003F3r 1  05 05 05 05  
0003F7r 1  05           
0003F8r 1  02 02 02 02  	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
0003FCr 1  02 02 02 02  
000400r 1  02           
000401r 1               bank_d500:
000401r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000405r 1  05 05 05 05  
000409r 1  05           
00040Ar 1  02 02 02 02  	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
00040Er 1  02 02 02 02  
000412r 1  02           
000413r 1               bank_d600:
000413r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000417r 1  05 05 05 05  
00041Br 1  05           
00041Cr 1  02 02 02 02  	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID
000420r 1  02 02 02 02  
000424r 1  02           
000425r 1               bank_d700:
000425r 1  05 05 05 05  	.byte BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK, BANK_UNK
000429r 1  05 05 05 05  
00042Dr 1  05           
00042Er 1  02 02 02 02  	.byte BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_SID, BANK_RAM, BANK_SID, BANK_SID
000432r 1  02 02 00 02  
000436r 1  02           
000437r 1               
000437r 1               
000437r 1               test_turbo:
000437r 1  A2 rr A0 rr  	STRING test_turbo_str
00043Br 1  20 rr rr     
00043Er 1               
00043Er 1               	; Enter configuration mode for this test
00043Er 1  A9 2A        	lda	#42
000440r 1  8D FE D0     	sta	CFGENA
000443r 1               
000443r 1  A9 00        	lda	#0
000445r 1  8D rr rr     	sta	turbo_idx
000448r 1  8D F3 D0     	sta	CFGTUR
00044Br 1               
00044Br 1               	; Turbo is off and every option disabled
00044Br 1               	; Turbo bit must be invisible at D030 and not influence the turbo functionality
00044Br 1               	;
00044Br 1  AD 30 D0     	lda	$D030
00044Er 1  C9 FF        	cmp	#$ff
000450r 1  20 rr rr     	jsr	redgreen_hex
000453r 1               
000453r 1  A9 00        	lda	#$00
000455r 1  8D 30 D0     	sta	$D030
000458r 1  AD 30 D0     	lda	$D030
00045Br 1  C9 FF        	cmp	#$ff
00045Dr 1  20 rr rr     	jsr	redgreen_hex
000460r 1  AD F3 D0     	lda	CFGTUR
000463r 1  C9 00        	cmp	#$00
000465r 1  20 rr rr     	jsr	redgreen_hex
000468r 1               ;	jsr	test_show_turbo
000468r 1               
000468r 1  A9 01        	lda	#$01
00046Ar 1  8D 30 D0     	sta	$D030
00046Dr 1  AD 30 D0     	lda	$D030
000470r 1  C9 FF        	cmp	#$ff
000472r 1  20 rr rr     	jsr	redgreen_hex
000475r 1  AD F3 D0     	lda	CFGTUR
000478r 1  C9 00        	cmp	#$00
00047Ar 1  20 rr rr     	jsr	redgreen_hex
00047Dr 1               ;	jsr	test_show_turbo
00047Dr 1               
00047Dr 1               	; Enable turbo bit at D030
00047Dr 1               	; Turbo bit must be visible at D030 and allow control of the turbo
00047Dr 1               	;
00047Dr 1  20 rr rr     	jsr	space
000480r 1  A9 20        	lda	#$20
000482r 1  8D F3 D0     	sta	CFGTUR
000485r 1               
000485r 1  AD 30 D0     	lda	$D030
000488r 1  C9 FE        	cmp	#$fe
00048Ar 1  20 rr rr     	jsr	redgreen_hex
00048Dr 1               
00048Dr 1  A9 01        	lda	#$01
00048Fr 1  8D 30 D0     	sta	$D030
000492r 1  AD 30 D0     	lda	$D030
000495r 1  C9 FF        	cmp	#$ff
000497r 1  20 rr rr     	jsr	redgreen_hex
00049Ar 1  AD F3 D0     	lda	CFGTUR
00049Dr 1  C9 A0        	cmp	#$A0
00049Fr 1  20 rr rr     	jsr	redgreen_hex
0004A2r 1               ;	jsr	test_show_turbo
0004A2r 1               
0004A2r 1  A9 00        	lda	#$00
0004A4r 1  8D 30 D0     	sta	$D030
0004A7r 1  AD 30 D0     	lda	$D030
0004AAr 1  C9 FE        	cmp	#$fe
0004ACr 1  20 rr rr     	jsr	redgreen_hex
0004AFr 1  AD F3 D0     	lda	CFGTUR
0004B2r 1  C9 20        	cmp	#$20
0004B4r 1  20 rr rr     	jsr	redgreen_hex
0004B7r 1               
0004B7r 1               
0004B7r 1               	; Test all the available speed options of the turbo
0004B7r 1               	;
0004B7r 1  A2 06 20 rr  	SPACES 6
0004BBr 1  rr           
0004BCr 1               
0004BCr 1               	; 1x speed
0004BCr 1  A9 00        	lda	#$00
0004BEr 1  8D F3 D0     	sta	CFGTUR
0004C1r 1  20 rr rr     	jsr	test_show_turbo
0004C4r 1               	; 2x speed
0004C4r 1  A9 82        	lda	#$82
0004C6r 1  8D F3 D0     	sta	CFGTUR
0004C9r 1  20 rr rr     	jsr	test_show_turbo
0004CCr 1               	; 3x speed
0004CCr 1  A9 83        	lda	#$83
0004CEr 1  8D F3 D0     	sta	CFGTUR
0004D1r 1  20 rr rr     	jsr	test_show_turbo
0004D4r 1               	; 4x speed
0004D4r 1  A9 84        	lda	#$84
0004D6r 1  8D F3 D0     	sta	CFGTUR
0004D9r 1  20 rr rr     	jsr	test_show_turbo
0004DCr 1               	; 5x speed
0004DCr 1  A9 85        	lda	#$85
0004DEr 1  8D F3 D0     	sta	CFGTUR
0004E1r 1  20 rr rr     	jsr	test_show_turbo
0004E4r 1               	; 6x speed
0004E4r 1  A9 86        	lda	#$86
0004E6r 1  8D F3 D0     	sta	CFGTUR
0004E9r 1  20 rr rr     	jsr	test_show_turbo
0004ECr 1               	; Unlimited speed
0004ECr 1  A9 80        	lda	#$80
0004EEr 1  8D F3 D0     	sta	CFGTUR
0004F1r 1  20 rr rr     	jsr	test_show_turbo
0004F4r 1  A2 05 20 rr  	SPACES 5
0004F8r 1  rr           
0004F9r 1               
0004F9r 1               	; 25% speed
0004F9r 1  A9 8F        	lda	#$8F
0004FBr 1  8D F3 D0     	sta	CFGTUR
0004FEr 1  20 rr rr     	jsr	test_show_turbo
000501r 1               	; 50% speed
000501r 1  A9 8E        	lda	#$8E
000503r 1  8D F3 D0     	sta	CFGTUR
000506r 1  20 rr rr     	jsr	test_show_turbo
000509r 1               	; 75% speed
000509r 1  A9 8D        	lda	#$8D
00050Br 1  8D F3 D0     	sta	CFGTUR
00050Er 1  20 rr rr     	jsr	test_show_turbo
000511r 1               	; 100% speed
000511r 1  A9 8C        	lda	#$8C
000513r 1  8D F3 D0     	sta	CFGTUR
000516r 1  20 rr rr     	jsr	test_show_turbo
000519r 1               
000519r 1  60           	rts
00051Ar 1               
00051Ar 1               
00051Ar 1               test_show_turbo:
00051Ar 1  20 rr rr     	jsr	space
00051Dr 1               
00051Dr 1               	; Copy turbo routine to 0300 to always have the same fixed position.
00051Dr 1               	; As the test code can change alignment issues can influence the test results
00051Dr 1  A2 00        	ldx	#$00
00051Fr 1               test_show_turbo1:
00051Fr 1  BD rr rr     	lda	test_turbo_speed,x
000522r 1  9D 00 03     	sta	$0300,x
000525r 1  E8           	inx
000526r 1  D0 F7        	bne test_show_turbo1
000528r 1               
000528r 1  20 00 03     	jsr	$0300
00052Br 1  98           	tya
00052Cr 1  AC rr rr     	ldy	turbo_idx
00052Fr 1  D9 rr rr     	cmp	turbo_cmp,y
000532r 1  20 rr rr     	jsr	redgreen_hex
000535r 1  EE rr rr     	inc	turbo_idx
000538r 1  8A           	txa
000539r 1  4C rr rr     	jmp	printhex
00053Cr 1               
00053Cr 1               test_turbo_speed:
00053Cr 1  A2 00        	ldx	#$00
00053Er 1  A0 00        	ldy	#$00
000540r 1               test_turbo_speed1:
000540r 1  AD 12 D0     	lda	RASTER
000543r 1  C9 F1        	cmp	#$F1
000545r 1  D0 F9        	bne	test_turbo_speed1
000547r 1               
000547r 1               test_turbo_speed2:
000547r 1  AD 12 D0     	lda	RASTER
00054Ar 1  C9 F0        	cmp	#$F0
00054Cr 1  F0 07        	beq	test_turbo_speed_end
00054Er 1  EA           	nop
00054Fr 1  E8           	inx
000550r 1  D0 F5        	bne	test_turbo_speed2
000552r 1  C8           	iny
000553r 1  D0 F2        	bne	test_turbo_speed2
000555r 1               test_turbo_speed_end:
000555r 1  60           	rts
000556r 1               
000556r 1               turbo_idx:
000556r 1  00           	.byte	0
000557r 1               turbo_cmp:
000557r 1  04 0E 12 17  	.byte	$04, $0E, $12, $17, $1C, $24, $24	; no,2x,3x,4x,5x,6x,unlim
00055Br 1  1C 24 24     
00055Er 1  01 02 03 04  	.byte	$01, $02, $03, $04                  ; 25,50,75,100 percent
000562r 1               
000562r 1               
000562r 1               coreid_str:
000562r 1  43 6F 72 65  	.byte   "CoreID: ",0
000566r 1  49 44 3A 20  
00056Ar 1  00           
00056Br 1               version_str:
00056Br 1  20 20 56 65  	.byte   "  Version: '",0
00056Fr 1  72 73 69 6F  
000573r 1  6E 3A 20 27  
000578r 1               startup_str:
000578r 1  53 74 61 72  	.byte	"Startup CFGENA=", 0
00057Cr 1  74 75 70 20  
000580r 1  43 46 47 45  
000588r 1               startup_cfgtur_str:
000588r 1  2C 43 46 47  	.byte	",CFGTUR=",0
00058Cr 1  54 55 52 3D  
000590r 1  00           
000591r 1               startup_cfgreg_str:
000591r 1  2C 43 46 47  	.byte	",CFGREG=",0
000595r 1  52 45 47 3D  
000599r 1  00           
00059Ar 1               test_cfgena_str:
00059Ar 1  54 65 73 74  	.byte	"Test CFGENA: ",0
00059Er 1  20 43 46 47  
0005A2r 1  45 4E 41 3A  
0005A8r 1               test_cfgreg_str:
0005A8r 1  54 65 73 74  	.byte	"Test CFGREG: ",0
0005ACr 1  20 43 46 47  
0005B0r 1  52 45 47 3A  
0005B6r 1               test_turbo_str:
0005B6r 1  54 65 73 74  	.byte	"Test Turbo: ",0
0005BAr 1  20 54 75 72  
0005BEr 1  62 6F 3A 20  
0005C3r 1               hextbl:
0005C3r 1  30 31 32 33  	.byte	"0123456789ABCDEF"
0005C7r 1  34 35 36 37  
0005CBr 1  38 39 41 42  
0005D3r 1               
0005D3r 1               clear_screen:
0005D3r 1  A2 00        	ldx	#$00
0005D5r 1               clear_screen1:
0005D5r 1  A9 20        	lda	#$20
0005D7r 1  9D 00 04     	sta	REGENPOS,x
0005DAr 1  9D 00 05     	sta	REGENPOS+$0100,x
0005DDr 1  9D 00 06     	sta	REGENPOS+$0200,x
0005E0r 1  9D 00 07     	sta	REGENPOS+$0300,x
0005E3r 1  A5 FB        	lda	COLOR
0005E5r 1  9D 00 D8     	sta	COLORRAM,x
0005E8r 1  9D 00 D9     	sta	COLORRAM+$0100,x
0005EBr 1  9D 00 DA     	sta	COLORRAM+$0200,x
0005EEr 1  9D 00 DB     	sta	COLORRAM+$0300,x
0005F1r 1  E8           	inx
0005F2r 1  D0 E1        	bne	clear_screen1
0005F4r 1               
0005F4r 1  A9 00        	lda	#<REGENPOS
0005F6r 1  85 FE        	sta CURSORL
0005F8r 1  A9 04        	lda	#>REGENPOS
0005FAr 1  85 FF        	sta CURSORH
0005FCr 1  A9 00        	lda	#<COLORRAM
0005FEr 1  85 FC        	sta COLORL
000600r 1  A9 D8        	lda	#>COLORRAM
000602r 1  85 FD        	sta COLORH
000604r 1  60           	rts
000605r 1               
000605r 1               
000605r 1               
000605r 1               printstr:
000605r 1  86 F9        	stx	STRINGL
000607r 1  84 FA        	sty	STRINGH
000609r 1  A0 00        	ldy	#$00
00060Br 1               printstr1:
00060Br 1  B1 F9        	lda	(STRINGL),y
00060Dr 1  F0 0B        	beq	printstr_e
00060Fr 1  20 rr rr     	jsr	print_char
000612r 1  E6 F9        	inc	STRINGL
000614r 1  D0 F5        	bne	printstr1
000616r 1  E6 FA        	inc	STRINGH
000618r 1  D0 F1        	bne	printstr1
00061Ar 1               printstr_e:
00061Ar 1  60           	rts
00061Br 1               
00061Br 1               printhex:
00061Br 1  48           	pha
00061Cr 1  4A           	lsr
00061Dr 1  4A           	lsr
00061Er 1  4A           	lsr
00061Fr 1  4A           	lsr
000620r 1  20 rr rr     	jsr	printnibble
000623r 1  68           	pla
000624r 1               printnibble:
000624r 1  29 0F        	and	#$0f
000626r 1  8E rr rr     	stx	print_tempx
000629r 1  AA           	tax
00062Ar 1  BD rr rr     	lda	hextbl,x
00062Dr 1  AE rr rr     	ldx	print_tempx
000630r 1  4C rr rr     	jmp	print_char
000633r 1               print_tempx:
000633r 1  00           	.byte	0
000634r 1               
000634r 1               redgreen:
000634r 1  48           	pha
000635r 1  F0 06        	beq	redgreen2
000637r 1  A9 02        	lda	#RED_COLOR
000639r 1               redgreen1:
000639r 1  85 FB        	sta	COLOR
00063Br 1  68           	pla
00063Cr 1  60           	rts
00063Dr 1               redgreen2:
00063Dr 1  A9 05        	lda	#GRN_COLOR
00063Fr 1  D0 F8        	bne	redgreen1
000641r 1               redgreen_hex:
000641r 1  20 rr rr     	jsr	redgreen
000644r 1  20 rr rr     	jsr	printhex
000647r 1  A9 0E        	lda	#DEF_COLOR
000649r 1  85 FB        	sta	COLOR
00064Br 1  60           	rts
00064Cr 1               
00064Cr 1               print_spaces:
00064Cr 1  20 rr rr     	jsr	space
00064Fr 1  CA           	dex
000650r 1  D0 FA        	bne	print_spaces
000652r 1  60           	rts
000653r 1               space:
000653r 1  A9 20        	lda	#$20
000655r 1               print_char:
000655r 1  8C rr rr     	sty	print_tempy
000658r 1  A0 00        	ldy	#$00
00065Ar 1  91 FE        	sta	(CURSORL),y
00065Cr 1  A5 FB        	lda	COLOR
00065Er 1  91 FC        	sta	(COLORL),y
000660r 1  E6 FE        	inc	CURSORL
000662r 1  E6 FC        	inc	COLORL
000664r 1  D0 04        	bne	print_char_e
000666r 1  E6 FF        	inc	CURSORH
000668r 1  E6 FD        	inc	COLORH
00066Ar 1               print_char_e:
00066Ar 1  AC rr rr     	ldy	print_tempy
00066Dr 1  60           	rts
00066Er 1               print_tempy:
00066Er 1  00           	.byte	0
00066Er 1